1. Field of the Invention
This invention relates to a semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a workload (load) subjected to a process to be performed and, for example, applied to an LSI used for a portable equipment and having a cache SRAM incorporated therein.
2. Description of the Related Art
In LSIs used for portable equipment, a method for dynamically controlling the operation frequency (clock) and power supply voltage according to a load subjected to a process to be performed in order to suppress the power consumption is used. When a process for a heavy load is performed, the power supply voltage is enhanced and the operation frequency is enhanced to cope with the process with high power and high speed. On the other hand, when a process for a light load is performed, the power consumption is suppressed by lowering the power supply voltage and lowering the operation frequency. In order to attain the operation of lowering the power consumption of the LSI using the above method, it is important to set the operation voltage as low as possible at the light-load time.
However, it becomes difficult to perform the low-voltage operation of an SRAM often used as a cache memory element in the LSI with a reduction in the device based on the scaling rule.
For example, as is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2006-073065, a six-transistor SRAM cell is configured by a pair of PMOS load transistors, a pair of NMOS drive transistors and a pair of NMOS transfer transistors. One of the PMOS load transistors and one of the NMOS drive transistors are combined to configure a CMOS inverter. Likewise, the other one of the PMOS load transistors and the other one of the NMOS drive transistors are combined to configure a CMOS inverter. The input terminals and output terminals of the two CMOS inverters are cross-coupled to configure a flip-flop circuit to store data. The current paths of the pair of NMOS transfer transistors are respectively connected between the storage nodes of the flip-flop circuit and paired bit lines. A word line is connected to the gates of the NMOS transfer transistors to select the cell.
When the cell is not selected, the word line is set at a low potential level and the pair of NMOS transfer transistors are made to not conduct (turned off). As a result, one of the storage nodes holds the power supply voltage VDD and the other storage node holds the ground potential VSS. On the other hand, when the cell is selected, the word line is set at a high potential level, the pair of NMOS transfer transistors are made to conduct (turned on) and the potentials of the paired bit lines vary according to the potentials of the storage nodes. The potential variation in the paired bit lines is amplified by means of a sense amplifier and stored data is read.
At this time, since both of the paired bit lines are generally precharged to the power supply voltage VDD, the potential of one of the storage nodes which is set at the lower level (ground potential VSS) is slightly pulled up via the NMOS transfer transistor. At this time, if a variation (rise) in the potential level of the storage node is large and exceeds the threshold voltage of the flip-flop circuit, the state of the flip-flop circuit is inverted and stored data will be destroyed.
The degree of the rise in the level of the storage node is determined based on the ratio of the pull-down ability of the NMOS drive transistor to the pull-up ability of the NMOS transfer transistor. Therefore, in order to stabilize the cell, it is important to make the β ratio of the NMOS drive transistor and the NMOS transfer transistor large.
There occurs a problem due to a large variation in the characteristics of elements with miniaturization of each element based on the scaling rule. In order to prevent occurrence of data destruction even when the characteristics vary, it is necessary to securely attain a sufficiently high β ratio. When the operation voltage is lowered, the influence of the characteristic variation becomes relatively larger. Therefore, it is necessary to set a sufficiently high β ratio in order to stably operate the cell on the low voltage.
However, when the size (channel width) of the NMOS drive transistor in the SRAM cell is increased in order to increase the β ratio, the pattern-occupied area is increased. Recently, the rate of the area of the cache SRAM which occupies the chip becomes increasingly higher as the LSI is made to have highly sophisticated functions. Therefore, an increase in the cell area gives a large influence on the chip size. In order to reduce the chip size, it is necessary to set the SRAM cell as small as possible and it becomes difficult to securely attain a sufficiently high β ratio. Thus, there occurs a problem that the operation voltage of the SRAM section cannot be lowered and the power consumption at the light-load time cannot be sufficiently suppressed.